How to Reduce Noise from Chip?

In this tutorial we are going to learn about How to Reduce Noise from Chip?

The following applies to pins that are used for simple digital I/O, not for pins used in the memory-

Expansion bus. The main aim here is not so much to reduce the noise of the edge switching, but to mute the noise of the clock glitches when the pin is static. When the Noise on the pins is coupled internal to the device through many paths that can change as the pin function changes. For example, the input pin in a keyboard scan has capacitive coupled noise from both the substrate & the PWR rails. Also, because it is hi-z, any ambient fields couple efficiently. If the key is pushed, then the pin has a new set of noise sources because the signal line’s impedance has changed. Thus, it is difficult to effectively develop a matrix of all possibilities; therefore, the following is recommended:

• Put a 50 –100- W resistor in series with every o/p pin & 35W–50W resistor on every i/p pin. When the system design calls for higher series resistance, use that value. Higher resistances are better for o/ps, but usually don’t improve characteristics of inputs. Place the resistor as close as possible to the microcomputer, overlapping the microcomputer GND if possible.

• Bypass any pin on the microcomputer to GND using a 1000-pF capacitor, provided the edge rate needed for the signal line is not faster than 100 ns. On o/p & pins that the system uses for both I/O, GND for the capacitor should be the microcomputer GND. The second end of the capacitor should be tied to the receiver side, not the microcomputer side, of the series resistor. Placement of the capacitor inside the resistor makes the load seen by the microcomputer look like a short when it switches, which is not desirable. When adding the capacitor has to be traded off against placing the series resistor, because of space limitations, place only the resistor.

• Always used on pins used for input only, place the capacitor inside, on the microcomputer side, of the resistor to reduce the loop area. Then, HF originating in the microcomputer on the pin see less impedance to GND through the capacitor than through the resistor.

• Reset & interrupt are special functions, thus care must be taken not to reduce functionality.

• Don’t apply any of the above remedies to oscillator pins. If proper spacing between the oscillator components & other unrelated components & traces is maintained, there shouldn’t be a need for oscillator signal conditioning.

• Unused pins should be configured as inputs & tied directly to the microcomputer GND. It is recommended that the watchdog be enabled to correct the unlikely event in which a device is disturbed, loses its program counter, & executes code to make the input become an output with a high level. These rules take up space & add components, & so are not well accepted in production. The goal is to implement all rules on all I/O pins, but if that is not possible, then rank order the candidates least likely to cause noise & reduce the application of the rules one pin at a time.

• Signals leaving the enclosure.

• Signals avoid the PCB to other boards inside the enclosure.

• Signals flow on the PCB with high-impedance loads (i.e., driving another MOS input or open circuit)

• Pins of parallel I/O port designed to support high speed data transfer, e.g., between the microcomputer & an external memory, need filtering over the remaining I/O pins, because of their faster rise & fall times. When the design is complete & first prototypes are built, an hour or 2 in the screen room removing each of the filtering components one at a time, identifies that are or are not needed to get the desired EMI level.

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