In this tutorial we are going to learn about How to Select Trace Dimension For PCB Design.
Squeezing trace tightly together increase the circuit packing density very dense designs require fewer circuit board layers since printed circuit board cost is proportional to the number of layers as well as to the board surface area we are tempted to always design using the fewest number of layers that will do the job. If have traces are small then there will be more closely spaced traces also may be more crosstalk and less power-handling capacity this tradeoff among crosstalk routing density and power is critical to low-cost product design ,Let’s deal with power-handling capacity first because it is simplest of the constraints .The power-handling capacity of a printed circuit trace depends mostly on its cross-sectional area and the allowable temperature rise for a given cross-sectional area trace’s temperature rises are unreliable and heat up nearby digital circuits a conservative upper limit on trace heating inside digital products is 10oC. As per image of relates maximum power-handling capacity to temperature rise the horizontal axis in image measures cross-sectional area in units of square inches the vertical axis of image showing the available current for that trace at a given temperature rise. For example a 0.010 –in-wide trace of 1-oz copper (0.00135 in thick) can safely pass 750 Ma of current at a temperature rise of 10oC. Power is rarely a serious constraint except for large power distribution buses as thin-film technology with extremely small trace cross sections becomes more widely available heating limitations may become more prevalent. A power bound on trace width results from the manufacturing process lists the minimum trace widths attainable in various production processes with any process the manufacturing yield will drop and cost will go up as one approach the minimum attainable trace width this factor prevents most designers from using the minimum attainable line width, Other factors tend to increase line width poor control over the etching process can result in large line large line width variations at low line widths the percentage line width variable which controls the percentage impedance tolerance may be unacceptable a need for accurate impedance control can force the use of lines much wider than the minimum attainable trace width. Use the formulas for trace impedance in appendix C to find a combination of trace width and height sufficiency large that over expected variations in which and layer height the impedance stays within your design range remember that you must also allot room in your impedance budget for variations in the electric permittivity of the substrate Considerations of power cost and impedance tolerance usually drive the selection of a particular trace width given the width the impedance constraint sets the layer height. Next using the formula for crosstalk figure the minimum spacing between adjacent traces this number is called the minimum trace pitch the unused distance between traces is called the trace separation the sum of the trace separation and the trace width equals the trace pitch.