In this tutorial we are going to learn about How to Stack Printed Circuit Board Layers
A layer stack for a printed circuit board specifies the arrangement of circuit board layer it specifies which layers are solid power and ground planes the dielectric constant of the substrate and the spacing’s between layers when planning a layer stack also compute the desired trace dimensions and minimum trace spacing
Manufacturing constrains heavily influence the layer stack as a rule the greater your circuit wiring density the greater your production costs per square inch this section sets out some basic rules of thumb for planning layer stack
Power and Ground planning
Design the power and ground layers first to plan a power and ground system first establish the signal rise times the number of signals and the physical dimension of the circuit board , Included among the physical dimensions make a guess as to the trace width the trace width assumption is not particularly critical at this stage Next estimate the self-inductance and mutual inductance using solid hatched and fingers ground plane models at this point it is usually clear which model suits the design remember that for the ground fingers model all traces interact for the hatched model traces running along the same hatch grid interact for the ground plane model only adjacent trace interact, If we will be using a solid ground plane plan on using ground and power plans in pairs the symmetric pairing of solid plans in a layer stack helps prevent warping in the circuit board a board with a single plane offset to one side can warp noticeably
Power plans may be used as low-inductance signal return-current path just as ground planes assuming adequate bypass capacitors between power and ground (chapter 8) transmission lines routed over a power plane operate as well as those routed over a ground plane transmission strap lines routed between one power and one ground layer or two power layers also work
Sometimes you will want to run a signal outside your digital system for this application you may pick a low –speed or controlled rise-time driver this is a good choice because it reduce external radiation which helps with FCC problems, If the ground for the driver connects to ordinary digital logic ground the effective driver output equal its intended drive voltage plus any noise present in the digital logic ground as per below image. Digital logic grounds are notorious for high- frequency noise voltage grounds carry fluctuating voltages caused by the action of many returning signal currents acting across their self-inductance these high-frequency fluctuations are too small to cause trouble in the digital circuits but plenty large enough to exceed FCC limits any wire connected to the digital logic ground which runs outside the cabinet almost always fails FCC tests without other precautions the controlled rise-time driver effectively picks up ground noise and broadcasts it outside the chassis.
One solution to this problem adds a chassis plane to the layer stack this plane stack directly next to a ground plane giving a very tight capacitive coupling between the two planes at high frequencies the two planes are effectively tied together the chassis plane then screws solders or welds to axis near the controlled rise-time driver at high frequencies we have effectively shorted the digital ground plane to the chassis this reduces the amount of digital ground noise at that point also reducing noise carried by the controlled rise-time driver to the outside word.
Ordinary capacitors will not function as a short between chassis and digital logic ground because they have too much lead inductance only the large wide parallel surface area between the chassis plane and digital ground plane has a low enough inductance to effectively short the two together with the chassis plane approach the digital logic and external chassis remain electrically isolated at low frequencies this may be describe for safety or other reasons if the isolation does not matter simply short digital logic ground directly to the chassis without using a separate chassis layer make this connection by screwing soldering or welding the ground plane to the external chassis with a continuous axis close to controlled rise-time driver, When using a chassis plane counterbalance it in the layer stack with some other solid plane layer for mechanical reasons always lawn toward using symmetric arrangements of plans in PCB layer stack